ICX418AKL
Diagonal 8mm (Type 1/2) CCD Image Sensor for NTSC Color Video Cameras
Description
20 pin DIP (Cer-DIP)
The ICX418AKL is an interline CCD solid-state
image sensor suitable for NTSC color video cameras
with a diagonal 8mm (Type 1/2) system. Compared
with the current product ICX038DNA, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. This chip is compatible with the pins of the
ICX038DNA and has the same drive conditions.
Pin 1
2
Features
V
3
• High sensitivity (+6.0dB compared with the ICX038DNA)
• Low smear (–5.0dB compared with the ICX038DNA)
• High D range (+2.0dB compared with the ICX038DNA)
• High S/N
12
H
40
Pin 11
• High resolution and low dark current
• Excellent antiblooming characteristics
• Ye, Cy, Mg, and G complementary color mosaic filters on chip
• Continuous variable-speed shutter
Optical black position
(Top View)
• Substrate bias:
Adjustment free (external adjustment also possible with 6 to 14V)
• Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V)
• Horizontal register: 5V drive
Device Structure
• Interline CCD image sensor
• Optical size:
Diagonal 8mm (Type 1/2)
• Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels
• Total number of pixels:
• Chip size:
811 (H) × 508 (V) approx. 410K pixels
7.40mm (H) × 5.95mm (V)
8.4µm (H) × 9.8µm (V)
• Unit cell size:
• Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction:
Horizontal 22
Front 12 pixels, rear 2 pixels
• Number of dummy bits:
Vertical 1 (even fields only)
Silicon
• Substrate material:
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E01503B41
ICX418AKL
Block Diagram and Pin Configuration
(Top View)
10
9
8
7
6
5
4
3
2
1
Cy
Cy
Mg
Cy
Ye
Ye
Mg
Cy
G
Ye
Mg
Ye
G
G
Ye
Mg
Ye
G
G
G
Cy
Mg
Cy
Mg
Note)
Horizontal Register
Note)
: Photo sensor
11
12
13
14
15
16
17
18
19
20
Pin Description
Pin No. Symbol
Description
Pin No. Symbol
Description
1
2
Vφ4
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate clock
11
12
13
14
15
16
17
18
19
20
NC
Vφ3
VDSUB
NC
Substrate bias circuit supply voltage
3
Vφ2
4
φSUB
GND
Vφ1
GND
GND
RD
GND
5
GND
GND
6
Vertical register transfer clock
Protective transistor bias
GND
Reset drain bias
Reset gate clock
7
VL
φRG
8
GND
VDD
VOUT
NC
9
Output circuit supply voltage
Signal output
Hφ1
Hφ2
Horizontal register transfer clock
Horizontal register transfer clock
10
– 3 –
ICX418AKL
Absolute Maximum Ratings
Item
Substrate clock φSUB – GND
Ratings
–0.3 to +50
–0.3 to +18
–55 to +10
–15 to +20
to +10
Unit
V
Remarks
VDD, VRD, VDSUB, VOUT – GND
V
Supply voltage
VDD, VRD, VDSUB, VOUT – φSUB
Vφ1, Vφ2, Vφ3, Vφ4 – GND
Vφ1, Vφ2, Vφ3, Vφ4 – φSUB
V
V
Clock input voltage
V
∗1
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ4
to +15
V
to +17
V
–17 to +17
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +30
–30 to +80
–10 to +60
V
φRG – GND
V
φRG – φSUB
V
VL – φSUB
V
Pins other than GND and φSUB – VL
Storage temperature
V
°C
°C
Operating temperature
∗1
+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
– 4 –
ICX418AKL
Bias Conditions 1 [when used in substrate bias internal generation mode]
Item
Output circuit supply voltage
Reset drain voltage
Symbol Min.
Typ. Max. Unit
Remarks
VDD
VRD
VL
14.55 15.0 15.45 V
14.55 15.0 15.45
V
V
VRD = VDD
∗1
Protective transistor bias
Substrate bias circuit supply voltage
Substrate clock
VDSUB
φSUB
14.55
15.45
15.0
∗2
∗1
VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗2
Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Bias Conditions 2 [when used in substrate bias external adjustment mode]
Item
Symbol Min.
Typ. Max. Unit
Remarks
Output circuit supply voltage
Reset drain voltage
VDD
14.55 15.0 15.45 V
VRD
14.55 15.0 15.45
V
VRD = VDD
∗3
∗4
Protective transistor bias
VL
Substrate bias circuit supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
VDSUB
VSUB
∆VSUB
∗5
∗5
6.0
–3
14.0
+3
V
%
∗3
VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
Connect to GND or leave open.
∗4
∗5
The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a
special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in
substrate bias internal generation mode.
VSUB code — one character indication
Code and optimal setting correspond to each other as follows.
VSUB code
E
f
G
h
J
K
L
m
N
P
Q
R
S
T
U
V
W
Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
<Example> "L" → VSUB = 9.0V
DC Characteristics
Item
Symbol Min.
Typ.
5.0
Max.
10.0
Unit
mA
Remarks
Output circuit supply current
IDD
– 5 –
ICX418AKL
Clock Voltage Conditions
Waveform
diagram
Item
Symbol
Min. Typ. Max. Unit
Remarks
Readout clock voltage VVT
14.55 15.0 15.45
V
V
V
1
2
2
VVH1, VVH2
VVH3, VVH4
–0.05
–0.2
0
0
0.05
0.05
VVH = (VVH1 + VVH2)/2
VVL1, VVL2,
VVL3, VVL4
–9.6 –9.0 –8.5
V
VVL = (VVL3 + VVL4)/2
2
VφV
8.3
9.0 9.65 Vp-p
Vφ = VVHn – VVLn (n = 1 to 4)
V
2
2
2
2
2
2
2
2
3
3
4
4
4
5
| VVH1 – VVH2 |
VVH3 – VVH
VVH4 – VVH
VVHH
0.1
0.1
0.1
0.5
0.5
0.5
0.5
V
V
V
V
V
V
V
Vertical transfer clock
voltage
–0.25
–0.25
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
VVHL
VVLH
VVLL
VφH
4.75 5.0 5.25 Vp-p
Horizontal transfer
clock voltage
VHL
–0.05
0
0.05
V
V
1
∗
VRGL
Reset gate clock
VφRG
4.5
5.0
5.5 Vp-p
0.8
23.0 24.0 25.0 Vp-p
∗1
voltage
VRGLH – VRGLL
VφSUB
V
Low-level coupling
Substrate clock voltage
∗1
Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Waveform
diagram
Item
Symbol
Min. Typ. Max. Unit
Remarks
VRGL
VφRG
–0.2
8.5
0
0.2
V
4
4
Reset gate clock
voltage
9.0
9.5 Vp-p
– 6 –
ICX418AKL
Clock Equivalent Circuit Constant
Symbol
CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφH1
Typ.
2700
2700
820
330
100
91
Item
Min.
Max. Unit
Remarks
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Capacitance between vertical transfer clock
and GND
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock
and GND
CφH2
CφHH
47
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
CφRG
11
CφSUB
680
91
R1, R3
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Ω
R2, R4
100
68
Ω
RGND
Vφ2
Vφ1
CφV12
R1
R2
Hφ1
Hφ2
CφHH
CφV1
CφV2
CφV41
CφV23
CφH2
CφH1
RGND
CφV3
CφV4
R4
R3
CφV34
Vφ4
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
– 7 –
ICX418AKL
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
VVT
φM
φM
2
10%
0%
0V
tr
twh
tf
(2) Vertical transfer clock waveform
Vφ1
Vφ3
VVH1
VVHH
VVHH
VVH
VVH
VVHH
VVHH
VVHL
VVHL
VVHL
VVHL
VVH3
VVL1
VVL3
VVLH
VVLH
VVLL
VVLL
VVL
VVL
Vφ2
Vφ4
VVHH
VVHH
VVH4
VVHH
VVHH
VVH
VVH
VVHL
VVHL
VVHL
VVHL
VVH2
VVLH
VVL2VVLH
VVLL
VVLL
VVL4
VVL
VVL
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
– 8 –
ICX418AKL
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
VφH
twl
10%
VHL
tr
twh
tf
(4) Reset gate clock waveform
VRGH
twl
VφRG
Point A
RG waveform
VRGL + 0.5V
VRGL
VRGLH
VRGLL
VRGLm
Hφ1
waveform
+2.5V
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the period twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
φM
VφSUB
φM
2
10%
VSUB
0%
tr
twh
tf
– 9 –
ICX418AKL
Clock Switching Characteristics
twh
twl
tr
tf
Symbol
VT
Item
Unit
Remarks
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Readout clock
2.3 2.5
0.5
0.5
15
µs During readout
Vertical transfer Vφ1, Vφ2,
∗1
250 ns
clock
Vφ3, Vφ4
During
imaging
∗2
Hφ
20
20
15 19
15 19 ns
During
parallel-serial
conversion
5.38
0.01
0.01
0.01
µs
Hφ1
5.38
51
0.01
Hφ2
ns
µs
11 13
1.5 1.8
3
3
Reset gate clock φRG
When draining
charge
φSUB
0.5
0.5
Substrate clock
∗1
∗2
When vertical transfer clock driver CXD1267AN is used.
tf ≥ tr – 2ns.
two
Symbol
Item
Horizontal transfer clock
Unit Remarks
∗3
Min. Typ. Max.
16 20
Hφ1, Hφ2
ns
∗3
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
– 10 –
ICX418AKL
Image Sensor Characteristics
Item Symbol Min.
Sensitivity
(Ta = 25°C)
Measurement
method
Typ.
Max. Unit
Remarks
S
1040
1000
1300
mV
mV
1
2
3
4
4
5
5
6
7
8
8
8
9
9
9
9
10
Saturation signal
Smear
Ysat
Sm
Ta = 60°C
–115
–105
20
25
10
10
2
dB
%
Zone 0 and I
SHy
Video signal shading
%
Zone 0 to II'
∆Sr
∆Sb
Ydt
∆Ydt
Fy
%
Uniformity between
video signal channels
%
mV
mV
%
Ta = 60°C
Ta = 60°C
Dark signal
Dark signal shading
Flicker Y
1
2
Fcr
5
%
Flicker R-Y
Flicker B-Y
Line crawl R
Line crawl G
Line crawl B
Line crawl W
Lag
Fcb
Lcr
5
%
3
%
Lcg
Lcb
Lcw
Lag
3
%
3
%
3
%
0.5
%
Zone Definition of Video Signal Shading
768 (H)
14
14
12
V
10
H
8
H
8
494 (V)
Zone 0, I
Zone II, II'
10
Ignored region
Effective pixel region
V
10
Measurement System
∗
[ Y]
Y signal output
∗
[ A]
CCD signal output
LPF1
(3dB down 6.3MHz)
CCD
C.D.S
AMP
∗
[ C]
S/H
S/H
LPF2
(3dB down 1MHz)
Chroma signal output
∗
∗
∗
∗
Note) Adjust the amplifier gain so that the gain between [ A] and [ Y], and between [ A] and [ C] equals 1.
– 11 –
ICX418AKL
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the
value indicated on the device.)
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output
or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
Cy
G
Ye
Mg
Ye
G
Cy
G
Ye
Mg
Ye
G
As shown in the left figure, fields are read out. The charge is
mixed by pairs such as A1 and A2 in the A field. (pairs such
as B in the B field)
A1
A2
B
Cy
Mg
Cy
Mg
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).
Hreg
Color Coding Diagram
These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} × 1/2
= 1/2 {2B + 3G + 2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} × 1/2
= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:
– (B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)
in alternation. This is also true for the B field.
– 12 –
ICX418AKL
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and
image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard
sensitivity testing luminous intensity.
2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.
250
60
S = Ys ×
[mV]
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of the Y signal output, 200mV, measure the minimum value of the Y signal.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula.
1
500
1
10
YSm
200
Sm = 20 × log
×
×
[dB] (1/10V method conversion value)
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.
SHy = (Ymax – Ymin)/200 × 100 [%]
5. Uniformity between video signal channels
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin
[mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the
following formula.
∆Sr = | (Crmax – Crmin)/200 | × 100 [%]
∆Sb = | (Cbmax – Cbmin)/200 | × 100 [%]
6. Dark signal
Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
– 13 –
ICX418AKL
7. Dark signal shading
After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Ydt = Ydmax – Ydmin [mV]
8. Flicker
1) Fy
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]). Then
substitute the value into the following formula.
Fy = (∆Yf/200) × 100 [%]
2) Fcr, Fcb
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between
fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr, CAb).
Substitute the values into the following formula.
Fci = (∆Ci/CAi) × 100 [%] (i = r, b)
9. Line crawls
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the
following formula.
Lci = (∆Yli/200) × 100 [%] (i = w, r, g, b)
10. Lag
Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following
formula.
Lag = (Ylag/200) × 100 [%]
FLD
V1
Light
Strobe light
timing
Y signal output 200mV
Ylag (lag)
Output
– 14 –
Drive Circuit 1 (substrate bias internal generation mode)
15V
1
2
20
19
18
17
16
15
14
13
12
11
100k
3
1
1/35V
4
XSUB
XV2
–9V
5
CXD1267AN
3.3/16V
6
XV1
7
XSG1
XV3
22/16V
1M
8
9
XSG2
XV4
10
22/20V
0.01
3.3/20V
1
2
3
4
5
6
7
8
9
10
ICX418
(BOTTOM VIEW)
20 19 18 17 16 15 14 13 12 11
Hφ1
0.01
Hφ2
100
∗
[ A]
CCD OUT
3.9k
0.01
RG
Drive Circuit 2 (substrate bias external adjustment mode)
15V
270k
0.1
15k
47k
1
2
20
19
18
17
16
15
14
13
12
11
56k
1/35V
1/35V
15k
1/35V
100k 27k
39k
0.1
3
0.1
4
XSUB
XV2
–9V
5
CXD1267AN
3.3/16V
6
XV1
7
XSG1
XV3
22/16V
1M
8
9
XSG2
XV4
10
22/20V
0.01
3.3/20V
1
2
3
4
5
6
7
8
9
10
ICX418
(BOTTOM VIEW)
20 19 18 17 16 15 14 13 12 11
Hφ1
0.01
Hφ2
100
∗
[ A]
CCD OUT
3.9k
0.01
RG
ICX418AKL
Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics)
1.0
0.8
0.6
0.4
0.2
0
Cy
Ye
G
Mg
400
450
500
550
Wave Length [nm]
600
650
700
Sensor Readout Clock Timing Chart
V1
V2
2.5
Odd Field
V3
V4
1.6
2.5 2.5 2.5
33.5
0.2
V1
V2
Even Field
V3
V4
Unit: µs
– 17 –
Drive Timing Chart (Vertical Sync)
FLD
VD
BLK
HD
V1
V2
V3
V4
1 3 5
2 4 6
2 4
1 3 5
6
493
494
494
493
2 4 6
1 3 5
1 3 5
2 4 6
CCD
OUT
Drive Timing Chart (Horizontal Sync)
HD
BLK
H1
H2
RG
V1
V2
V3
V4
SUB
ICX418AKL
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
39N
29N
29N
0.9Nm
Upper ceramic
Low melting
point glass
Lower ceramic
Compressive strength
Shearing strength
Tensile strength
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.
– 20 –
ICX418AKL
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not to
perform the following actions as this may cause cracks.
• Applying repeated bending stress to the outer leads.
• Heating the outer leads for an extended period with a soldering iron.
• Rapidly cooling or heating the package.
• Applying any load or impact to a limited portion of the low melting point glass using tweezers or other
sharp tools.
• Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.
Note that the same cautions also apply when removing soldered products from boards.
e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
– 21 –
Package Outline
Unit: mm
20pin DIP (600mil)
A
0.7
(1.0)
(1.7)
9.0
20
11
11
20
(0.7R)
φ1.4
C
B
V
H
10
1
10
1
18.0 ± 0.4
B'
3
14.6
1. “A” is the center of the effective image area.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
~
3. The bottom “C” of the package is the height reference.
4. The center of the effective image area, relative to “B” and “B'” is
(H, V) = (9.0, 7.55) ± 0.15mm.
1.778
0.46
0.8
5. The rotation angle of the effective image area relative to H and V is ± 1˚.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.
7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
9. The notch and the hole on the bottom must not be used for reference of fixing.
0.4
M
0.3
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
Cer-DIP
TIN PLATING
42 ALLOY
2.6g
PACKAGE MASS
DRAWING NUMBER
AS-B14-01(E)
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